11. External bus xBUS

11.1 External bus registers

External bus auxiliary setting register (XBUS_AUX):

Bit	Name	Access	Description
7	bUART0_TX	R0	Indicate the transmission status of UART0, 1 means it is transmitting
6	bUART0_RX	R0	Indicate the receiving status of UART0, 1 means it is receiving
5	bSAFE_MOD_ACT	R0	Indicate the safe mode status, 1 means that it is currently in safe mode
4	bALE_CLK_EN	RW	ALE pin clock output enable, this bit is 1 to allow ALE to output the system's main frequency of 12 when there is no xBUS operation, that is, Fsys / 12; this bit is 0 to disable the output of clock signals and only output when necessary to access the external bus Low 8-bit address latch signal to reduce EMI
3	GF2	RW	General flag bit 2: user can define by himself, can be cleared or set by software
2	bDPTR_AUTO_INC	RW	Enable auto-increment DPTR by 1 after the MOVX_@DPTR instruction is completed
1	reserved	R0	reserved
0	DPS	RW	Dual DPTR data pointer selection bits: This bit is 0 to select DPTR0. This bit is 1 to select DPTR1

External bus speed configuration register (XBUS_SPEED):

Bit	Name	Access	Description	Reset value
7	bXBUS1_SETUP	RW	Select XBUS1 settling time: if this bit is 0, then 2 clock cycles. If this bit is 1, then 3 clock cycles	1
6	bXBUS1_HOLD	RW	Select XBUS1 hold time: if this bit is 0, it will take 1 clock cycle. If this bit is 1, it will take 2 clock cycles	1
5	bXBUS1_WIDTH1	RW	XBUS1 bus pulse width high	1
4	bXBUS1_WIDTH0	RW	XBUS1 bus pulse width low bit	1
3	bXBUS0_SETUP	RW	Select XBUS0 settling time: If this bit is 0, it will take 2 clock cycles. If this bit is 1, it will take 3 clock cycles	1
2	bXBUS0_HOLD	RW	Select XBUS0 hold time: if this bit is 0, it will take 1 clock cycle. If this bit is 1, it will take 2 clock cycles	1
1	bXBUS0_WIDTH1	RW	XBUS0 bus pulse width high order	1
0	bXBUS0_WIDTH0	RW	XBUS0 bus pulse width low bit	1

11.2 External bus pins

Table 11.2.1 External bus pin list

GPIO	Direct Address Mode Pin	Multiplexed Address Mode Pin	Description
P3.7	RD	RD	External bus read signal output pin, active low, rising edge sampling input
P3.6	WR	WR	External bus write signal output pin, active low
P0.0~P0.7	D0~D7	D0~D7	8-bit bidirectional data bus
P0.0~P0.7		A0~A7	Multiplex lower 8-bit address A [0:7] output, latched by external circuit controlled by ALE
P4.0~P4.5	A0~A5	Unused	Direct bus address A [0: 5] output pin, P4_DIR output must be set
P3.5	A6	Unused	Bus direct address A6 output pin
P2.7	A7		Bus direct address A7 output pin
P2.7		A15	Bus address A15 output pin
P2.0~P2.6	A8~A14	A8~A14	Bus address A [8:14] output pin
P3.4	XCS0	XCS0	Chip select 0 output pin, address range 4000h~7FFFh, active low
P3.3	!A15	!A15	Bus address A15 inverting output pin, equivalent to chip select 1 output, address range 8000h~FFFFh, active low, only available in ALE disabled state
P5.5	!A15	!A15	Bus address A15 inverting output pin, equivalent to chip select 1 output, address range 8000h~FFFFh, active low, available only in ALE enabled state
P5.4		ALE	Multiplexed low 8-bit address latch control output pin, active high
P5.4	ALE		System frequency 12-division clock Fsys / 12 output pin, duty cycle 1/12

Some of the above unused pins such as address output and chip select output in the external bus state can be used for other modules according to the GPIO multiplexing priority order, and the unused pins in P4.0~P4.5 can also be used. Set P4_DIR to keep the input status.

When bXBUS_CS_OE = 1, the inverting signal of bus address A15 will select the output pin according to the ALE output status. When ALE is allowed to output, !A15 chooses to output from P5.5. When ALE is disabled to output, !A15 chooses from P3.3 output. The ALE output status is determined by the combination of bUH1_DISABLE, bXBUS_EN, bXBUS_AL_OE, and bALE_CLK_EN, refer to Table 11.2.2 below.

Table 11.2.2 P5.4 Pin Multiplexing ALE Output Status Table

bUH1_DISABLE	bXBUS_EN	bXBUS_AL_OE	bALE_CLK_EN	P5.4 pin function description
0	x	x	x	Disable ALE output, priority as HM (P5.5 as HP)
1	0	x	0	Disable ALE output, used as XB by default (P5.5 as XA)
1	0	x	1	ALE only outputs the system's 12th-frequency clock signal
1	1	1	0	Disable ALE output, default for XB (P5.5 is used as XA)
1	1	1	1	ALE only outputs the system's 12th-frequency clock signal
1	1	0	0	ALE outputs the lower 8-bit address latch signal only on the bus
1	1	0	1	ALE outputs the lower 8-bit address latch signal when accessing the bus, and outputs the system's main frequency 12-frequency clock signal when idle