12. Timer

12. Timer

12.1 Timer 0/1

Timer0 / 1 are two 16-bit timer / counters. TCON and TMOD are used to configure Timer0 and Timer1. TCON is used for timer / counter T0 and T1 start control and overflow interrupt and external interrupt control. Each timer is a 16-bit timing unit consisting of two 8-bit registers. The high byte counter of timer 0 is TH0, the low byte is TL0; the high byte counter of timer 1 is TH1, and the low byte is TL1. Timer 1 can also be used as a baud rate generator for UART0.

Table 12.1.1 List of Timer 0/1 related registers

NameAddressDescriptionReset value
TH18DhTimer1 count high bytexxh
TH08ChTimer0 count high bytexxh
TL18BhTimer1 count low bytexxh
TL08AhTimer0 count low bytexxh
TMOD89hTimer0 / 1 mode register00h
TCON88hTimer0 / 1 control register00h

Timer/Counter 0/1 Control Register (TCON):

BitNameAccessDescriptionReset value
7TF1RWTimer1 overflow interrupt flag bit, it is automatically cleared after entering Timer 1 interrupt0
6TR1RWTimer1 start / stop bit, set to 1 to start, set or cleared by software0
5TF0RWTimer0 overflow interrupt flag bit, enters timer 0 and is automatically cleared after interrupt0
4TR0RWTimer0 start / stop bit, set to 1 to start, set or cleared by software0
3IE1RWINT1 Interrupt request flag bit for external interrupt 1; it is automatically cleared after entering interrupt0
2IT1RWINT1 External interrupt 1 trigger mode control bit. This bit is 0 to select the external interrupt to trigger at low level. This bit is 1 to select the external interrupt to trigger at falling edge.0
1IE0RWINT0 Interrupt request flag for external interrupt 0. It is automatically cleared after entering interrupt0
0IT0RWINT0 External interrupt 0 trigger mode control bit. This bit is 0 to select the external interrupt to trigger at low level. This bit is 1 to select the external interrupt to trigger at falling edge.0

Timer/Counter 0/1 Mode Register (TMOD):

BitNameAccessDescriptionReset value
7bT1_GATERWThe gate enable bit controls whether Timer1 start is affected by external interrupt signal INT1. If this bit is 0, whether Timer/Counter 1 is started has nothing to do with INT1. If this bit is 1, it can be started only when INT1 pin is high and TR1 is 10
6bT1_CTRWTiming or counting mode selection bit, this bit is 0 to work in timing mode. This bit is 1 to work in counting mode, using the falling edge of T1 pin as clock0
5bT1_M1RWTimer/Counter 1 mode selection high0
4bT1_M0RWTimer/Counter 1 mode selection low0
3bT0_GATERWGating enable bit, controls whether Timer0 start is affected by external interrupt signal INT0. If this bit is 0, the timer/counter 0 is started regardless of INT0. If this bit is 1, only the INT0 pin is high and TR0 can be started0
2bT0_CTRWTiming or counting mode selection bit, this bit is 0 to work in timing mode; this bit is 1 to work in counting mode, using the falling edge of T0 pin as clock0
1bT0_M1RWTimer/Counter 0 Mode selection high0
0bT0_M0RWTimer/Counter 0 Mode selection low0

Table 12.1.2 bTn_M1 and bTn_M0 select Timern operating mode (n = 0, 1)

bTn_M1bTn_M0Timern working mode (n = 0, 1)
00Mode 0: 13-bit timer / counter n. The counting unit consists of the lower 5 bits of TLn and THn. The upper 3 bits of TLn are invalid. When the count changes from all 13 bits to all 0s, the overflow flag TFn is set and the initial value needs to be reset
01Mode 1: 16-bit timer / counter n. The counting unit consists of TLn and THn. When the count changes from all 16 bits to all 0s, the overflow flag TFn is set and the initial value needs to be reset
10mode 2: 8-bit reload timer / counter n, the counting unit uses TLn, THn as the reload counting unit. When the count changes from all 8 bits to all 0s, the overflow flag TFn is set and the initial value is automatically loaded from THn
11Mode 3: If it is timer / counter 0, then timer / counter 0 is divided into two parts TL0 and TH0, TL0 is used as an 8-bit timer / counter and occupies all control bits of Timer0; and TH0 also serves as another 8-bit timer Use, occupy TR1, TF1 and interrupt resources of Timer1, and Timer1 is still available at this time, but the start control bit TR1 and overflow flag bit TF1 cannot be used. In the case of Timer / Counter 1, entering Mode 3 will stop Timer / Counter 1.

Timern count low byte (TLn) (n = 0, 1):

BitNameAccessDescriptionReset value
[7:0]TLnRWTimern count low bytexxh

Timern count high byte (THn) (n = 0, 1):

BitNameAccessDescriptionReset value
[7:0]TLnRWTimern count high bytexxh

12.2 Timer2

Timer2 is a 16-bit auto-reload timer/counter. It is configured through the T2CON and T2MOD registers. The high byte counter of timer 2 is TH2 and the low byte is TL2. Timer2 can be used as the baud rate generator of UART0. It also has two signal level capture functions. The capture count is stored in RCAP2 and T2CAP1 registers.

Table 12.2.1 List of Timer2 related registers

NameAddressDescriptionReset value
TH2CDhTimer2 Counter High Byte00h
TL2CChTimer2 counter low byte00h
T2COUNTCChTL2 and TH2 form 16-bit SFR0000h
T2CAP1HCDhTimer2 Capture 1 data high byte (read only)xxh
T2CAP1LCChTimer2 capture 1 data low byte (read only)xxh
T2CAP1CChT2CAP1L and T2CAP1H form a 16-bit SFRxxxxh
RCAP2HCBhCount Reload/Capture 2 Data Register High Byte00h
RCAP2LCAhCount Reload/Capture 2 Data Register Low Byte00h
RCAP2CAhRCAP2L and RCAP2H form a 16-bit SFR0000h
T2MODC9hTimer2 mode register00h
T2CONC8hTimer2 Control Register00h

Timer/Counter 2 Control Register (T2CON):

BitNameAccessDescriptionReset value
7TF2RWWhen bT2_CAP1_EN = 0, it is the overflow interrupt flag of Timer2. When Timer2 counts from 16 bits are all 1 to all 0, setting the overflow flag to 1 requires software to clear it; when RCLK = 1 or TCLK When = 1, this bit will not be set to 10
7CAP1FRWWhen bT2_CAP1_EN = 1, it is Timer2 capture 1 interrupt flag, which is triggered by the valid edge of T2 and needs to be cleared by software0
6EXF2RWTimer2 external trigger flag. When EXEN2 = 1, it is set by T2EX valid edge trigger. Need to be cleared by software.0
5RCLKRWUART0 receive clock selection, this bit is 0 to select the baud rate generated by Timer1 overflow pulse; this bit is 1 to select the baud rate generated by Timer2 overflow pulse0
4TCLKRWUART0 transmit clock selection, this bit is 0 to select the baud rate generated by Timer1 overflow pulse; this bit is 1 to select the baud rate generated by Timer2 overflow pulse0
3EXEN2RWT2EX trigger enable bit, this bit is 0 to ignore T2EX. This bit is 1 to enable triggering reload or capture on T2EX valid edge0
2TR2RWTimer2 start / stop bit, set to 1 to start, set or cleared by software0
1C_T2RWTimer2 clock source selection bit, this bit is 0 to use the internal clock; this bit is 1 to use the edge count based on the falling edge of the T2 pin0
0CP_RL2RWTimer2 function selection bit. If RCLK or TCLK is 1, this bit should be forced to 0. If this bit is 0, Timer2 is used as a timer / counter, and it can automatically reload the initial count value when the counter overflows or the T2EX level changes; this bit is 1 to enable the capture 2 function of Timer2 and capture the valid edge of T2EX0

Timer/Counter 2 Mode Register (T2MOD):

BitNameAccessDescriptionReset value
7bTMR_CLKRWThe fast clock mode enable of the T0 / T1 / T2 timer of the fast clock has been selected. If this bit is 1, the system clock Fsys without frequency division is used as the count clock. If this bit is 0, the frequency division clock is used. This bit has no effect on the timer that selects the standard clock0
6bT2_CLKRWTimer2 internal clock frequency selection bit. This bit is 0 to select the standard clock. The timing / counting mode is Fsys / 12. UART0 clock mode is Fsys / 4. This bit is 1 to select the fast clock. = 0) or Fsys (bTMR_CLK = 1), the UART0 clock mode is Fsys / 2 (bTMR_CLK = 0) or Fsys (bTMR_CLK = 1)0
5bT1_CLKRWTimer1 internal clock frequency selection bit. This bit is 0 to select the standard clock Fsys / 12. For 1 to select the fast clock Fsys / 4 (bTMR_CLK = 0) or Fsys (bTMR_CLK = 1)0
4bT0_CLKRWTimer0 internal clock frequency selection bit. This bit is 0 for the standard clock Fsys / 12. For 1 it is the fast clock Fsys / 4 (bTMR_CLK = 0) or Fsys (bTMR_CLK = 1)0
3bT2_CAP_M1RWTimer2 capture mode high

Capture mode selection:

X0: from falling edge to falling edge

01: From any edge to any edge, that is, the level changes

11: from rising edge to rising edge

0
2bT2_CAP_M0RWTimer2 capture mode low0
1T2OERWTimer2 clock output enable bit, this bit is 0 to disable the output. This bit is 1 to enable the T2 pin output clock, the frequency is half of the Timer2 overflow rate0
0bT2_CAP1_ENRWCapture 1 mode is enabled when RCLK = 0, TCLK = 0, CP_RL2 = 1, C_T2 = 0, T2OE = 0, this bit is 1 to enable capture 1 function to capture the valid edge of T2. This bit is 0 to disable capture 10

Count Reload / Capture 2 Data Register (RCAP2):

BitNameAccessDescriptionReset value
[7:0]RCAP2HRWHigh byte of reload value in timer / counter mode. High byte of timer captured by CAP2 in capture mode00h
[7:0]RCAP2LRWLow byte of reload value in timer / counter mode. Low byte of timer captured by CAP2 in capture mode00h

Timer2 counter (T2COUNT), only valid when bT2_CAP1_EN = 0:

BitNameAccessDescriptionReset value
[7:0]TH2RWHigh byte of current counter00h
[7:0]TL2RWLow byte of current counter00h

Timer2 capture 1 data (T2CAP1), only valid when bT2_CAP1_EN = 1:

BitNameAccessDescriptionReset value
[7:0]T2CAP1HRWHigh byte of timer captured by CAP1xxh
[7:0]T2CAP1LRWLow byte of timer captured by CAP1xxh

12.3 Timer3

Table 12.3.1 List of Timer3 related registers

NameAddressDescriptionReset value
T3_FIFO_HAFhFIFO high byte of Timer3xxh
T3_FIFO_LAEhFIFO low byte of Timer3xxh
T3_FIFOAEhT3_FIFO_L and T3_FIFO_H form a 16-bit SFRxxxxh
T3_DMA_AHADhDMA current buffer address high byte0xh
T3_DMA_ALAChDMA current buffer address low bytexxh
T3_DMAAChT3_DMA_AL and T3_DMA_AH form a 16-bit SFR0xxxh
T3_DMA_CNABhDMA Remaining Count Register00h
T3_CTRLAAhTimer3 Control Register02h
T3_STATA9hTimer3 status register00h
T3_END_HA7hTimer3 count end high bytexxh
T3_END_LA6hTimer3 low end byte countxxh
T3_ENDA6hT3_END_L and T3_END_H form a 16-bit SFRxxxxh
T3_COUNT_HA5hTimer3 current count high byte (read only)00h
T3_COUNT_LA4hTimer3 current count low byte (read only)00h
T3_COUNTA4hT3_COUNT_L and T3_COUNT_H form a 16-bit SFR0000h
T3_CK_SE_HA5hTimer3 clock division setting high byte00h
T3_CK_SE_LA4hTimer3 clock division setting low byte20h
T3_CK_SEA4hT3_CK_SE_L and T3_CK_SE_H form a 16-bit SFR0020h
T3_SETUPA3hTimer3 setting register04h

Timer3 setup register (T3_SETUP):

BitNameAccessDescriptionReset value
7bT3_IE_ENDRWThis bit is 1 to enable the capture mode count timeout interrupt or the PWM mode cycle end interrupt. This bit is 0 to disable the enable0
6bT3_IE_FIFO_OVRWThis bit is 1 to enable the FIFO overflow interrupt. This bit is 0 to disable the enable0
5bT3_IE_FIFO_REQRWThis bit is 1 to enable capture mode FIFO> = 4 interrupt or PWM mode FIFO <= 3 interrupt; this bit is 0 to disable enable0
4bT3_IE_ACTRWThis bit is 1 to enable the capture mode input signal to activate the interrupt or PWM mode data to trigger the interrupt; this bit is 1 to disable the enable0
3reserveR0reserve0
2bT3_CAP_INR0Input level of the current capture pin after noise filtering1
1bT3_CAP_CLKRWThis bit is 1 to enable input capture without minimum pulse width limitation.It is only valid when T3_CK_SE is 1.It is used to capture high speed signals.0
0bT3_EN_CK_SERWThis bit is 1 to enable access to the clock divider setting register; this bit is 0 to enable access to the current count register0

Timer3 current count (T3_COUNT), only valid when bT3_EN_CK_SE = 0:

BitNameAccessDescriptionReset value
[7:0]T3_COUNT_HROTimer3 current count high byte00h
[7:0]T3_COUNT_LROTimer3 current count low byte00h

Timer3 clock division setting register (T3_CK_SE), only valid when bT3_EN_CK_SE = 1:

BitNameAccessDescriptionReset value
[7:0]T3_CK_SE_HRWTimer3 clock divider high byte, only the lower 4 bits are valid, the upper 4 bits are fixed to 000h
[7:0]T3_CK_SE_LRWLow byte of Timer3 clock divider20h

Timer3 count end value register (T3_END):

BitNameAccessDescriptionReset value
[7:0]T3_END_HRWTimer3 count end high bytexxh
[7:0]T3_END_LRWTimer3 count end low bytexxh

Timer3 status register (T3_STAT):

BitNameAccessDescriptionReset value
7bT3_IF_DMA_ENDRWDMA Complete Interrupt Flag. A 1 in this bit indicates an interrupt. A 0 in this bit indicates no interrupt. Cleared on write 1 or cleared on T3_DMA_CN0
6bT3_IF_FIFO_OVRWA 1 in this bit indicates a FIFO overflow interrupt. A 0 in this bit indicates no interrupt. Write 1 clear0
5bT3_IF_FIFO_REQRWWhen this bit is 1, it indicates that the FIFO data interrupt flag is requested. In capture mode, it is triggered by FIFO> = 4, and in PWM mode, it is triggered by FIFO <= 3. If this bit is 0, there is no interrupt. Write 1 clear0
4bT3_IF_ACTRWWhen bT3_IE_ACT = 1, this bit is 1 to indicate that the capture mode input signal activates the interrupt or the PWM mode data triggers the interrupt. This bit is 0 without interrupt. Cleared on write 1 or cleared when accessing FIFO0
4bT3_IF_ENDRWWhen bT3_IE_ACT = 0, this bit is 1 to indicate the capture mode count timeout interrupt or PWM mode cycle end interrupt. If this bit is 0, there is no interrupt. Write 1 clear0
[3:0]MASK_T3_FIFO_CNTR0Timer3's current FIFO count0000b

Timer3 control register (T3_CTRL):

BitNameAccessDescriptionReset value
7bT3_CAP_M1RWTimer3 capture edge mode high. PWM data repeat mode high0
6bT3_CAP_M0RWTimer3 capture edge mode low bit. PWM data repeat mode high bit0
5bT3_PWM_POLARRWPWM output polarity control bit in PWM mode. If this bit is 0, the default low level is valid, and the high level is valid.If this bit is 1, the default high level is active, and the low level is valid.0
5bT3_CAP_WIDTHRWIn capture mode, the minimum capture pulse width setting bit. If this bit is 0, at least 4 frequency division clock cycles are valid.0
4bT3_DMA_ENRWThis bit is 1 to enable Timer3's DMA and DMA interrupts. 0 to disable it0
3bT3_OUT_ENRWThis bit is 1 to enable the PWM output of Timer3. This bit is 0 to disable0
2bT3_CNT_ENRWThis bit is 1 to enable Timer3 counting. This bit is 0 to pause counting0
1bT3_CLR_ALLRWThis bit is 1 to clear the Timer3 count and FIFO, which needs to be cleared by software1
0bT3_MOD_CAPRWTimer3 mode selection bit. If this bit is 0, Timer3 works in timer/count or PWM mode.If this bit is 1, it works in capture mode.0

In capture mode, bT3_CAP_M1 and bT3_CAP_M0 select the capture edge: when bT3_CAP_M1 and bT3_CAP_M0 are 00, the capture mode is turned off or suspended; when it is 01, the edge is activated by any edge, that is, the change in level, and the capture is from any edge to any edge; when it is 10 Activated by falling edge, capture from falling edge to falling edge. When it is 11, activate by rising edge, capture from rising edge to rising edge.

In PWM mode, bT3_CAP_M1 and bT3_CAP_M0 select the number of data repetitions: When bT3_CAP_M1 and bT3_CAP_M0 are 00, the data is not reused, that is, a new data is used every PWM cycle. When it is 01, the data is reused 4 times, that is, the same data is used for continuous 4 PWM cycles. When it is 10, the data is reused 8 times. When it is 11, the data is reused 16 times.

DMA remaining count register (T3_DMA_CN):

BitNameAccessDescriptionReset value
[7:0]T3_DMA_CNRWThe current remaining DMA count, which can be preset to the initial value, and is automatically reduced after the DMA operation00h

DMA current buffer address (T3_DMA):

BitNameAccessDescriptionReset value
[7:0]T3_DMA_AHRWThe current high byte of the DMA address, which can be preset to the initial value. It automatically increases after DMA. Only the lower 4 bits are valid. The upper 4 bits are fixed to 0. Only the first 4K of xRAM are supported.0xh
[7:0]T3_DMA_ALRWLow byte of the current DMA address, which can be preset to the initial value. It is automatically increased after DMA. Only the upper 7 bits are valid. The lowest bit is fixed at 0. Only even addresses are supported.xxh

FIFO port (T3_FIFO):

BitNameAccessDescriptionReset value
[7:0]T3_FIFO_HRWFIFO high byte of Timer3xxh
[7:0]T3_FIFO_LRWFIFO low byte of Timer3xxh

12.4 PWM Function

Timer3 of CH559 has a 16-bit PWM function. In addition, there are two other 8-bit PWMs. The PWM can choose the default output polarity to be low or high. It can dynamically modify the PWM output duty cycle. After the simple RC resistor and capacitor perform integral low-pass filtering, various output voltages can be obtained, which is equivalent to a low-speed digital-to-analog converter DAC.

PWM3 output duty cycle = T3_FIFO / T3_END, the support range is 0% to 100%. If the value of T3_FIFO is greater than T3_END, it is treated as 100%.

PWM1 output duty cycle = PWM_DATA / PWM_CYCLE, support range 0% to 100%, if the value of PWM_DATA is greater than PWM_CYCLE, it will be treated as 100%.

PWM2 output duty cycle = PWM_DATA2 / PWM_CYCLE, the support range is 0% to 100%. If the value of PWM_DATA2 is greater than PWM_CYCLE, it is treated as 100%.

In practical applications, it is recommended to allow the PWM pin output and set the PWM output pin to push-pull output mode.

12.4.1 PWM1 and PWM2

Table 12.4.1 List of PWM1 and PWM2 related registers

NameAddressDescriptionReset value
PWM_CYCLE9Fh3xxh
PWM_CK_SE9Eh300h
PWM_CTRL9Dh302h
PWM_DATA9Ch3xxh
PWM_DATA29Bh3xxh

PWM2 data register (PWM_DATA2):

BitNameAccessDescriptionReset value
[7:0]PWM_DATA2RWStore current data of PWM2, duty cycle of PWM2 output active level = PWM_DATA2 / PWM_CYCLExxh

PWM1 data register (PWM_DATA):

BitNameAccessDescriptionReset value
[7:0]PWM_DATARWStore the current data of PWM1, the duty cycle of PWM1 output active level = PWM_DATA / PWM_CYCLExxh

PWM control register (PWM_CTRL):

BitNameAccessDescriptionReset value
7bPWM_IE_ENDRWThis bit is 1 to enable the end of the PWM cycle or the MFM buffer empty interrupt0
6bPWM2_POLARRWWhen bPWM_MOD_MFM = 0, control the output polarity of PWM2. When this bit is 0, the default low level is valid, and the high level is valid. When the bit is 1, it is default high level and the low level is active0
6bMFM_BUF_EMPTYR0When bPWM_MOD_MFM = 1, this bit is 1 to indicate that the MFM buffer is empty0
5bPWM_POLARRWControls the polarity of PWM1 output. If this bit is 0, it defaults to low level, and the high level is valid. If this bit is 1, it defaults to high level, and the low level is valid.0
4bPWM_IF_ENDRWPWM cycle end interrupt flag bit, this bit is 1 means there is an interrupt, cleared by writing 1 or cleared by writing PWM_CYCLE or cleared when reloading data0
3bPWM_OUT_ENRWPWM1 output enable, this bit is 1 to enable PWM1 output0
2bPWM2_OUT_ENRWWhen bPWM_MOD_MFM = 0, this bit is 1 to enable PWM2 output0
2bMFM_BIT_CNT2R0When bPWM_MOD_MFM = 1, it indicates the current MFM encoding progress. This bit is 0 to indicate that the lower 4 bits are being processed. A 1 indicates that the upper 4 bits are being processed.0
1bPWM_CLR_ALLRWThis bit is 1 to clear the PWM1 and PWM2 counts and FIFOs and needs to be cleared by software1
0bPWM_MOD_MFMRWMFM encoding mode is enabled, this bit is 0 for PWM mode. This bit is 1 for MFM mode0

PWM clock division setting register (PWM_CK_SE):

BitNameAccessDescriptionReset value
[7:0]PWM_CK_SERWSetting the PWM Clock Divisor00h

PWM cycle period register (PWM_CYCLE):

BitNameAccessDescriptionReset value
[7:0]PWM_CYCLERWSet the PWM cycle period, when the value is 00h, it means 100hxxh

12.5 Timer Function

12.5.1 Timer0/1

  1. Set T2MOD to select the internal clock frequency of the timer. If bTn_CLK (n = 0/1) is 0, then the clock corresponding to Timer0/1 is Fsys/12; if bTn_CLK is 1, then select Fsys by bTMR_CLK = 0 or 1. / 4 or Fsys as the clock.
  2. Set the TMOD to configure the working mode of the timer.
  3. Set the timer/counter initial values TLn and THn (n = 0/1).
  4. Set the bit TRn (n = 0/1) in TCON to start or stop the timer/counter. It can be queried by bit TFn (n = 0/1) or detected by interrupt mode.

Mode 0: 13-bit timer/counter

Timer_Mode_0

Figure 12.5.1.1 Timer0/1 Mode 0

Mode 1: 16-bit timer/counter

Timer_Mode_1

Figure 12.5.1.2 Timer0/1 Mode 1

Mode 2: Automatic reload 8-bit timer/counter

Timer_Mode_2

Figure 12.5.1.3 Timer0/1 Mode 2

Mode 3: Timer0 is decomposed into two independent 8-bit timers and counters, and the TR1 control bit of Timer1 is borrowed. Timer1 replaces the borrowed TR1 control bit by whether to start mode 3, Timer1 enters mode 3, and Timer1 stops running.

Timer_Mode_3

Figure 12.5.1.4 Timer0 Mode 3

12.5.2 Timer2

Timer2 16-bit reload timer/counter mode:

  1. Set the bits RCLK and TCLK in T2CON to 0, and select the non-serial port baud rate generator mode.
  2. Set bit C_T2 in T2CON to 0. Select to use the internal clock, go to step (3). Can also set to 1 to select the falling edge of the T2 pin as the count clock, skip step (3).
  3. Set T2MOD to select the internal clock frequency of the timer. If bT2_CLK is 0, the clock of Timer2 is Fsys / 12. If bT2_CLK is 1, then select Fsys / 4 or Fsys as the clock by T.R_CLK = 0 or 1.
  4. Set the bit CP_RL2 of T2CON to 0 and select the 16-bit reload timer / counter function of Timer2.
  5. Set RCAP2L and RCAP2H to the reload value after the timer overflows, set TL2 and TH2 to the initial value of the timer (generally the same as RCAP2L and RCAP2H), set TR2 to 1, and t.rt Timer2.
  6. The current timer / counter status can be obtained by querying the TF2 or timer 2 interrupts.

Timer2_16bit

Figure 12.5.2.1 Timer2 16-bit reload timer/counter

Timer2 clock output mode:

Refer to the 16-bit reload timer / counter mode, and then set bit T2OE in T2MOD to 1 to enable the output of the TF2 frequency divided clock from the T2 pin.

Timer2 serial port 0 baud rate generator mode:

  1. Set bit C_T2 in T2CON to 0 to choose to use the internal clock or set it to 1 to select the falling edge of the T2 pin as the clock. Set the RCLK and TCLK in T2CON to 1 or one of h.m as required. selecting the baud rate generator mode.
  2. Set T2MOD to select the internal clock frequency of the timer. If bT2_CLK is 0, then the clock of Timer2 is Fsys / 4. If bT2_CLK is 1, then bTMR_CLK = 0 or 1 selects Fsys / 2 or Fsys as the clock. (3) Set RCAP2L and RCAP2H to the reload value after the timer overflows, set TR2 to 1, and start Timer2.

Timer2_baud_gen

Figure 12.5.2.2 Timer2 UART0 Baud Rate Generator

Timer2 dual channel capture mode:

  1. Set the bits RCLK and TCLK in T2CON to 0, and select the non-serial port baud rate generator mode.
  2. Set the bit C_T2 in T2CON to 0. Select to use the internal clock and go to step (3); also set it to select the falling edge of the T2 pin as the count clock and skip step (3).
  3. Set T2MOD to select the internal clock frequency of the timer. If bT2_CLK is 0, the clock of Timer2 is Fsys/12. If bT2_CLK is 1, then select Fsys/4 or Fsys as the clock by T.R_CLK = 0 or 1.
  4. Set the bits bT2_CAP_M1 and bT2_CAP_M0 of T2MOD to select the corresponding edge capture mode.
  5. Set the bit CP_RL2 of T2CON to 1 to select the capture function of T2EX pin by Timer2.
  6. Set TL2 and TH2 to the initial values ​​of the timer, set TR2 to 1, and start Timer2.
  7. When the CAP2 capture is completed, RCAP2L and RCAP2H will save the current TL2 and TH2 count values ​​and set EXF2 to generate an interrupt.The next captured RCAP2L and RCAP2H i.l be between the last captured RCAP2L and RCAP2H The difference is the signal width between the two valid edges.
  8. If bit C_T2 in T2CON is 0 and bit bT2_CAP1_EN in T2MOD is 1, then the capture function of Timer2 on the T2 pin will be enabled at the same time. When CAP1 capture is completed, T2CAP1L and T2CAP1H will save the current TL2 and TH2 And the CAP1F bit is set to generate an interrupt.

tim2_capture_mode

Figure 12.5.2.3 Timer2 capture mode

12.5.3 Timer3

  1. Set the bit bT3_EN_CK_SE in T3_SETUP to 1, enable the Timer3 clock division setting register T3_CK_SE, set the division factor, and count the clock to Fsys / T3_CK_SE. Clear T._EN_CK_SE after the setting is completed.
  2. Set the T3_END counting end value or the total number of PWM cycles.
  3. Turn on interrupt enable in T3_SETUP as required.
  4. Set each control bit in T3_CTRL, select the mode, and clear bT3_CLR_ALL, set bT3_CNT_EN to start Timer3.
  5. Set T3_DMA_AL and T3_DMA_AH and T3_DMA_CN as required, set bT3_DMA_EN to enable the DMA function.

tim3_16bit_tpc

Figure 12.5.3.1 Timer3 16-bit timer/PWM/capture

Data format captured by Timer3:

Timer3 can be used to capture the width between two valid edges of the signal.The width is expressed by the divided clock count. During or after the capture, the width data can be obtained through DMA or directly reading the FIFO.The data is 16 bits. The most significant bit is the identification bit and the lower 15 bits are the width count. After signal capture is enabled, data will be generated every time a valid edge is detected or every timer overflows.Because the data generated at the first valid edge is the width from the time when signal capture is enabled, not two valid edges Width, so the first data captured is usually discarded.

(1). bT3_CAP_M1 and bT3_CAP_M0 = 11

The rising edge is valid, capturing the signal width from the rising edge to the rising edge, that is, the rising edge is activated. If the highest bit of the data is 1, it means that the signal width has overflowed the counting end value, that is, if the timing exceeds T3_END and the next rising edge has not been found, the width value must be added to the width of the next data whose highest bit is 0. The most significant bit is 0, which means that the width is the width between the end of a certain rising edge, and whether the lower 15 bits are accumulated forward according to whether the most significant bit of some previous data is 1. In this mode, it is recommended to set T3_END to detect ultra-wide signals or end signals for special purposes, and normal signals should not overflow.

For example, T3_END is set to 4000h, and the raw data sequence collected is as follows

1234h, 2345h, 0456h, C000h, C000h, 1035h, 3579h, C000h, 2468h, and 0987h are combined to obtain the interval between each rising edge: 1234h, 2345h, 0456h, 9035h, 3579h, 6468h, 0987h

(2). bT3_CAP_M1 and bT3_CAP_M0 = 10

Same as above, but the falling edge is valid, capturing the signal width from the rising edge to the falling edge, that is, the falling edge is activated.

(3). bT3_CAP_M1 and bT3_CAP_M0 = 01

Any edge is valid, capturing the signal width from any edge to any edge, that is, the level change is activated. If the highest bit of the data is 1, then the width is a high-level width, that is, from the rising edge to the falling edge. If the highest bit of the data is 0, then the width is a low-level width, that is, from the falling edge to the rising edge. The lower 15 bits after masking the most significant bits are width values counted by the divided clock. In this mode, it is recommended to set T3_END to a larger value to avoid timing overflow, but it must not exceed 15 digits of valid data.