13. Universal asynchronous transceiver UART

13.1 Introduction to UART

CH559 chip provides two full-duplex asynchronous serial ports: UART0 and UART1. UART0 is a standard MCS51 serial port. Its data reception and transmission are realized through SBUF access to physically separate transmit / receive registers. The data written to SBUF is loaded into the transmit register, and the read operation to SBUF corresponds to the receive buffer register.

UART1 is an enhanced asynchronous serial port with the following features:

Compatible with 16C550 asynchronous serial port and enhanced.
Support 5, 6, 7 or 8 data bits and 1 or 2 stop bits.
support odd, even, no parity, blank 0, flag 1 and other verification methods.
Programmable communication baud rate, supporting 115200bps and communication baud rate up to 3Mbps.
.Built-in independent transmit and receive buffers and 8-byte FIFO FIFO buffer, support 4 FIFO trigger levels.
Support MODEM modem signals CTS, DSR, RI, DCD, DTR, RTS, can be externally converted to RS232 level.
Support hardware flow control signals CTS and RTS automatic handshake and automatic transmission rate control, compatible with TL16C550C.
Support for serial frame error detection and Break line interval detection.
Built-in SIR infrared codec, support IrDA infrared communication with baud rate of 2400bps to 115200bps.
Supports full-duplex and half-duplex serial communication, and provides a status pin for switching RS485.
Built-in half-duplex differential transceiver, directly supports simple long-distance multi-machine communication similar to RS485 bus.
Support to preset the address when this machine is used as a slave, used to automatically match the data packets on the bus when multi-machine communication.

13.2 UART Register

Table 13.2.1 List of UART related registers

Name	Address	Description	Reset value
SBUF	99h	UART0 data register	xxh
SCON	98h	UART0 Control Register	00h
SER1_DLL	9Ah	UART1 baud rate divisor latch low byte	xxh
SER1_RBR	9Ah	UART1 data receive buffer register (read only)	xxh
SER1_THR	9Ah	UART1 data transmission holding register (write only)	xxh
SER1_FIFO	9Ah	UART1 data FIFO read and write register	xxh
SER1_DIV	97h	UART1 prescaler divisor register	xxh
SER1_ADDR	97h	UART1 bus address preset register	FFh
SER1_MSR	96h	Modem MODEM status register (read only)	F0h
SER1_LSR	95h	UART1 line status register (read only)	60h
SER1_MCR	94h	Modem MODEM control register	00h
SER1_LCR	93h	UART1 line control register	00h
SER1_IIR	92h	UART1 interrupt identification register (read only)	01h
SER1_FCR	92h	FIFO control register (write only)	00h
SER1_DLM	91h	UART1 baud rate divisor latch high byte	80h
SER1_IER	91h	UART1 interrupt enable register	00h

13.2.1 UART0 Register Description

UART0 control register (SCON):

Bit	Name	Access	Description
7	SM0	RW	UART0 working mode selection bit 0, this bit is 0 selects 8-bit data asynchronous communication; this bit is 1 selects 9-bit data asynchronous communication
6	SM1	RW	UART0 working mode selection bit 1, this bit is 0 to set the fixed baud rate. This bit is 1 to set the variable baud rate, generated by timer T1 or T2
5	SM2	RW	UART0 multi-machine communication control bit: When receiving data in modes 2 and 3, when SM2 = 1, if RB8 is 0, then RI is not set to 1, reception is invalid. If RB8 is 1, then RI is set to 1, reception is valid. When SM2 = 0 When RB8 is 0 or 1, RI is set when receiving data, and the reception is valid. In mode 1, if SM2 = 1, then the reception is valid only when a valid stop bit is received. In mode 0, SM2 Bit must be set to 0
4	REN	RW	UART0 enable reception control bit, this bit is 0 to disable reception; this bit is 1 to enable reception
3	TB8	RW	The 9th bit of the transmitted data. In modes 2 and 3, TB8 is used to write the 9th bit of the transmitted data, which can be a parity bit.In multi-machine communication, it is used to indicate whether the host sends an address byte Data byte, TB8 = 0 is data, TB8 = 1 is address
2	RB8	RW	The 9th bit of the received data, in modes 2 and 3, RB8 is used to store the 9th bit of received data. In mode 1, if SM2 = 0, then RB8 is used to store the received stop bit. In mode 0 Without using RB8
1	TI	RW	Send interrupt flag bit, which is set by hardware after a data byte is transmitted and needs to be cleared by software
0	RI	RW	Receive interrupt flag bit, which is set by hardware after a data byte is received and needs to be cleared by software

Table 13.2.1.1 UART0 working mode selection

SM0	SM1	Description
0	0	Mode 0, shift register mode, fixed baud rate is Fsys / 12
0	1	Mode 1, 8-bit asynchronous communication mode, variable baud rate, generated by timer T1 or T2
1	0	mode 2, 9-bit asynchronous communication mode, the baud rate is Fsys / 128 (SMOD = 0) or Fsys / 32 (SMOD = 1)
1	1	Mode 3, 9-bit asynchronous communication, variable baud rate, generated by timer T1 or T2

In modes 1 and 3, when RCLK = 0 and TCLK = 0, the UART0 baud rate is generated by timer T1. T1 should be set to mode 2 auto-reload 8-bit timer mode, bT1_CT and bT1_GATE must both be 0, divided into the following types of clock situations.

Table 13.2.1.2 Calculation formula of UART0 baud rate generated by T1

bTMR_CLK	bT1_CLK	SMOD	Description
1	1	0	TH1 = 256-Fsys/32/ baud rate
1	1	1	TH1 = 256-Fsys/16/ baud rate
0	1	0	TH1 = 256-Fsys/4/32/ baud rate
0	1	1	TH1 = 256-Fsys/4/16/ baud rate
X	0	0	TH1 = 256-Fsys/12/32/ baud rate
X	0	1	TH1 = 256-Fsys/12/16/ baud rate

In modes 1 and 3, when RCLK = 1 or TCLK = 1, the baud rate of UART0 is generated by timer T2. T2 should be set to 16-bit automatic re-carrier rate generator mode, C_T2 and CP_RL2 must both be 0, divided into the following types of clock situations.

Table 13.2.1.3 Calculation formula of UART0 baud rate generated by T2

bTMR_CLK	bT2_CLK	Description
1	1	RCAP2 = 65536-Fsys/16 / baud rate
0	1	RCAP2 = 65536-Fsys/2/16 / baud rate
X	0	RCAP2 = 65536-Fsys/4/16 / baud rate

UART0 data register (SBUF):

Bit	Name	Access	Description	Reset value
[7:0]	SBUF	RW	UART0 data register, including sending and receiving two physically separate registers. Writing data to SBUF corresponds to the transmit data register. Reading data from SBUF corresponds to the receive data register	xxh

UART1 data FIFO read and write register SER1_FIFO, including data receiving buffer register SER1_RBR and data transmission holding register SER1_THR two physically separate registers.

Data receive buffer register (SER1_RBR), only valid when bLCR_DLAB = 0:

Bit	Name	Access	Description	Reset value
[7:0]	SER1_RBR	RO	Serial port receive buffer register. If the bLSR_DATA_RDY bit of SER1_LSR is 1, you can read the received data from this register. If bFCR_FIFO_EN is 1, the data received from the serial port shift register is first stored in the receive FIFO and then passed This register reads	xxh

Data transmission holding register (SER1_THR), only valid when bLCR_DLAB = 0:

Bit	Name	Access	Description	Reset value
[7:0]	SER1_THR	WO	The serial port transmission holding register, including the transmission FIFO, is used to write the data to be transmitted. If bFCR_FIFO_EN is 1, the written data is first stored in the transmission FIFO and then output one by one through the transmission shift register	xxh

Interrupt enable register (SER1_IER), only valid when bLCR_DLAB = 0:

Bit	Name	Access	Description	Reset value
1	2	3	4	5
7	bIER_RESET	RW	Serial port software reset control bit. This bit is 1 to reset the serial port. This bit can be automatically cleared without software clear	0
6	bIER_EN_MODEM_O	RW	UART1 Modem signal output enable bit, this bit is 1 to enable MODEM signal RTS / DTR output, this bit is 0 to disable output	0
5	bIER_PIN_MOD1	RW	UART1 pin mode selection high	0
4	bIER_PIN_MOD0	RW	UART1 pin mode selection low	0
3	bIER_MODEM_CHG	RW	Modem input status change interrupt enable bit, this bit is 1 to enable the modem input status change interrupt. This bit is 0 to disable	0
2	bIER_LINE_STAT	RW	Receive line status interrupt enable bit, this bit is 1 to enable the receive line status interrupt. This bit is 0 to disable	0
1	bIER_THR_EMPTY	RW	Transmit Holding Register Empty Interrupt Enable Bit. This bit is 1 to enable the transmit holding register empty interrupt. This bit is 0 to disable.	0
0	bIER_RECV_RDY	RW	Received data interrupt enable bit, this bit is 1 to enable generation of receive data completion interrupt and subsequent timeout interrupt of received data, this bit is 0 disable	0

The pin mode of UART1 consists of both bIER_PIN_MOD1 and bIER_PIN_MOD0 and bUH1_DISABLE, bXBUS_CS_OE, bXBUS_AL_OE, bALE_CLK_EN are combined to select different configurations.Among them, the last four can be combined into RS485EN:

RS485EN = bUH1_DISABLE & ~ ( bXBUS_CS_OE & ~ bXBUS_AL_OE | bALE_CLK_EN )

RS485EN	bIER_PIN_MOD1	bIER_PIN_MOD0	Description
x	0	0	RXD1 uses pin P4.0, TXD1 disables output
0	1	0	RXD1 and TXD1 use pins P2.6 / RXD1 and P2.7 / TXD1 respectively
0	0	1	RXD1 and TXD1 use pins P4.0 / RXD1_ and P4.4 / TXD1_ respectively
0	1	1	RXD1 and TXD1 and TNOW use pins P2.6 and P2.7 and P2.5 respectively
1	1	0	RXD1 and TXD1 share iRS485 differential pins XA and XB
1	0	1	RXD1 and TXD1 use pins XA and XB together, TNOW uses pin P4.4
1	1	1	RXD1 and TXD1 use pins XA and XB together, TNOW uses pin P2.5

The last three configurations in the above table are iRS485 half-duplex communication mode.At this time, RS485EN = 1, RXD1 and TXD1 use iRS485 differential pins XA and XB together. Through the built-in half-duplex differential transceiver, it directly supports simple RS485 Long-distance multi-machine communication of the bus.

In iRS485 half-duplex communication mode, the following parameters need to be set:

Set bMCR_HALF in SER1_MCR to 1, half-duplex transceiver mode;
Set bUH1_DISABLE in UHUB1_CTRL to 1 to disable the HP / HM pin.

Interrupt Identification Register (SER1_IIR):

Bit	Name	Access	Description	Reset value
[7:6]	MASK_U1_IIR_ID	R0	FIFO enable flag, 11 means FIFO is enabled	00b
[5:4]	reserved	R0	reserved	00b
[3:0]	MASK_U1_IIR_INT	R0	UART1 interrupt status flag	0001b
0	bIIR_NO_INT	R0	UART1 is interrupt flag, it is 1 without interrupt. 0 is interrupt	1

The interrupt status of UART1 is composed of 4 bits, bIIR_INT_FLAG3, bIIR_INT_FLAG2, bIIR_INT_FLAG1, and bIIR_INT_FLAG0. MASK_U1_IIR_INT is used as the serial port interrupt flag of UART1. The specific interrupts are shown in the following table.

Name	Address	Interrupt type	Interrupt source	Clear interrupt method
U1_INT_SLV_ADDR	0Eh	Bus address match	Received 1 data is the serial bus address, and the address matches the preset value or broadcast address	Read SER1_IIR or disable multi-machine mode
U1_INT_LINE_STAT	06h	Receive line status	bLSR_OVER_ERR or bLSR_PAR_ERR or bLSR_FRAME_ERR or bLSR_BREAK_ERR	Read SER1_LSR
U1_INT_RECV_RDY	04h	Receive data available	The number of received bytes reaches the trigger point of the FIFO	Read SER1_RBR
U1_INT_RECV_TOUT	0Ch	Receive data timeout	Data has been received, but the next data has not been received for more than 4 data bytes	Read SER1_RBR
U1_INT_THR_EMPTY	02h	SER1_THR register is empty	The transmit holding register is empty, and bIER_THR_EMPTY changes from 0 to 1 to re-enable the interrupt	Read SER1_IIR or write SER1_THR
U1_INT_MODEM_CHG	00h	MODEM input change	△ CTS or △ DSR or △ RI or △ DCD	Read SER1_MSR
U1_INT_NO_INTER	01h	No interruption	Without interruption

FIFO control register (SER1_FCR):

Bit	Name	Access	Description	Reset value
7	bFCR_FIFO_TRIG1	W0	Receive FIFO interrupt and hardware flow control trigger point set high	0
6	bFCR_FIFO_TRIG0	W0	Receive FIFO interrupt and hardware flow control trigger point set low	0
[5:3]	reserved	R0	reserved	000b
2	bFCR_T_FIFO_CLR	W0	Send FIFO data clear enable bit, this bit is 1 to clear the data in the transmit FIFO (excluding the data being transmitted). This bit can be automatically cleared without software clearing	0
1	bFCR_R_FIFO_CLR	W0	Receive FIFO data clear enable bit, this bit is 1 to clear the data in the receive FIFO (excluding the data being received). This bit can be cleared automatically without software clearing	0
0	bFCR_FIFO_EN	W0	FIFO enable bit, this bit is 1 to enable FIFO; this bit is 0 to disable FIFO. After disabling FIFO, it is 16C450 compatible mode, which is equivalent to FIFO having only one byte depth.It is recommended to enable FIFO	0

bFCR_FIFO_TRIG1 and bFCR_FIFO_TRIG0 form MASK_U1_FIFO_TRIG, which is used to set the interrupt point of the receive FIFO and the trigger point of hardware flow control: 11 corresponds to 7 bytes, that is, the reception of full 7 bytes generates an interrupt that is available for receiving data. When = 1, the level of the RTS pin is automatically disabled. 10 corresponds to 4 bytes. 01 corresponds to 2 bytes. 00 corresponds to 1 byte.

Line Control Register (SER1_LCR):

Bit	Name	Access	Description
7	bLCR_DLAB	RW	Baud rate divisor latch access enable bit. This bit is 0 to enable access to the registers SER1_RBR, SER1_THR, SER1_IER, SER1_ADR. This bit is 1 to enable access to the registers SER1_DLL, SER1_DLM, SER1_DIV
6	bLCR_BREAK_EN	RW	Force BREAK line interval enable bit, this bit is 0, no BREAK output is generated. This bit is 1, force BREAK output
5	bLCR_PAR_MOD1	RW	High parity mode
4	bLCR_PAR_MOD0	RW	Low parity mode
3	bLCR_PAR_EN	RW	Parity enable bit. This bit is 0. There is no parity bit. This bit is 1 to allow parity check bits to be generated during transmission and received during reception.
2	bLCR_STOP_BIT	RW	Stop bit format setting bit, this bit is 0, there is a stop bit; this bit is 1, there are two stop bits
1	bLCR_WORD_SZ1	RW	Data word length set high
0	bLCR_WORD_SZ0	RW	Data word length set low

The combination of bLCR_PAR_MOD1 and bLCR_PAR_MOD0 sets the format of the parity bit when bLCR_PAR_EN is 1: 00 for odd parity, 01 for even parity, 10 for flag bit (MARK, set to 1), and 11 for blank bit (SPACE, cleared to 0) ).

The combination of bLCR_WORD_SZ1 and bLCR_WORD_SZ0 sets the word length of a single data without parity: 00 is 5 data bits, 01 is 6 data bits, 10 is 7 data bits, and 11 is 8 data bits.

MODEM control register (SER1_MCR):

Bit	Name	Access	Description
7	bMCR_HALF	RW	Half-duplex transmit / receive mode enable bit. This bit is 0 to disable the half-duplex transmit / receive mode and support full duplex. The bit is 1 to enter the automatic half-duplex transmit / receive mode. Sending takes priority. Receiving is suspended during transmission. For receiving
6	bMCR_TNOW	RW	RTS pin function selection bit, this bit is 0 for standard RTS output; this bit is 1 for TNOW output, and the state of output is being transmitted, which can be used to control the half-duplex mode of RS485.
5	bMCR_AUTO_FLOW	RW	CTS and RTS hardware automatic flow control enable bit, this bit is 0 to disable hardware flow control. This bit is 1 to enable hardware automatic flow control.After hardware flow control is enabled, the serial port will continue to send the next data only when the CTS pin input is active low, otherwise the serial port transmission will be suspended. After hardware flow control is enabled, if bMCR_RTS is 1, then when the receive FIFO is empty, The serial port will automatically activate the low-level RTS pin automatically. When the number of bytes received reaches the trigger point of the FIFO, the serial port will automatically invalidate the RTS pin and be able to activate the RTS pin again when the receive FIFO is empty. After enabling hardware flow control CTSA change in input state does not generate a MODEM state interrupt. By connecting your own CTS pin to the other's RTS pin and sending your own RTS pin to the other's CTS pin, you can implement hardware automatic rate control
4	bMCR_LOOP	RW	Test mode enable bit for internal loop, this bit is 0 to disable internal loop test. This bit is 1 to enable internal loop test. In the internal loop test mode, all external output pins of the serial port are inactive.TXD1 internally returns to RXD1, RTS internally returns to CTS, DTR internally returns to DSR, OUT1 internally returns to RI, and OUT2 internally returns to DCD.
3	bMCR_OUT2	RW	Serial port interrupt request output enable bit, this bit is 0 to disable the serial port interrupt request output, this bit is 1 to enable the serial port interrupt request output
2	bMCR_OUT1	RW	User-defined MODEM control bit, no actual output pin is connected, used for internal loop test, or as a general-purpose data bit
1	bMCR_RTS	RW	RTS pin output control bit. When this bit is 0, the RTS pin output is invalid (high level). When the bit is 1, the RTS pin output is valid (low level)
0	bMCR_DTR	RW	DTR pin output control bit. When this bit is 0, the DTR pin output is invalid (high level). When the bit is 1, the DTR pin output is valid (low level)

Line Status Register (SER1_LSR):

Bit	Name	Access	Description	Reset value
7	bLSR_ERR_R_FIFO	R0	Error flag of the receive FIFO. This bit is 1 indicating that there is at least one bLSR_PAR_ERR, bLSR_FRAME_ERR, or bLSR_BREAK_ERR error in the receive FIFO.	0
6	bLSR_T_ALL_EMP	R0	Transmit related register full empty flag bit, this bit is 1 means the transmit holding register SER1_THR and FIFO and transmit shift register are empty	1
5	bLSR_T_FIFO_EMP	R0	This bit is 1 to indicate that the transmit holding registers SER1_THR and FIFO are empty	1
4	bLSR_BREAK_ERR	R0	When this bit is 1, it indicates that BREAK line interval status is detected	0
3	bLSR_FRAME_ERR	R0	This bit is 1 to indicate that the current data in the receive FIFO is framing, and a valid stop bit is missing	0
2	bLSR_PAR_ERR	R0	This bit is 1 to indicate the parity error of the current data in the receive FIFO	0
1	bLSR_OVER_ERR	R0	This bit is 1 to indicate the receive FIFO buffer overflow	0
0	bLSR_DATA_RDY	R0	This bit is 1 to indicate that there is received data in the receive FIFO. After reading all the data in the FIFO, this bit is automatically cleared to 0	0

Modem MODEM status register (SER1_MSR):

Bit	Name	Access	Description	Reset value
7	bMSR_DCD	R0	This bit is the bit inversion of the DCD pin. A value of 1 indicates that the DCD pin is active (active low)	1
6	bMSR_RI	R0	This bit is the bit inversion of the RI pin. A 1 indicates that the RI pin is active (active low)	1
5	bMSR_DSR	R0	This bit is the bit inversion of the DSR pin. A value of 1 indicates that the DSR pin is active (active low)	1
4	bMSR_CTS	R0	This bit is the bit inversion of the CTS pin. A 1 indicates that the CTS pin is active (active low)	1
3	bMSR_DCD_CHG	R0	This bit is 1 to indicate that the input status of the DCD pin has changed.	0
2	bMSR_RI_CHG	R0	This bit is 1 to indicate that the input state of the RI pin has changed	0
1	bMSR_DSR_CHG	R0	This bit is 1 to indicate that the input state of the DSR pin has changed	0
0	bMSR_CTS_CHG	R0	This bit is 1 to indicate that the CTS pin input state has changed	0

UART1 bus address preset register (SER1_ADDR), only valid when bLCR_DLAB = 0:

Bit	Name	Access	Description	Reset value
[7:0]	SER1_ADDR	RW	Preset bus address for automatic comparison in multi-machine communication	FFh

SER1_ADDR presets the address when this machine is used as a slave. It is used to automatically compare the received addresses during multi-machine communication, and to generate an interrupt when the addresses match or when it receives the broadcast address 0FFH, and at the same time allow receiving subsequent data packets. Do not receive any data before the address does not match. After starting to send data or after rewriting the SER1_ADDR register, stop receiving any data until the next time the address matches again or the broadcast address is received.

When SER1_ADDR is 0FFH or bLCR_PAR_EN = 0, the automatic comparison of bus addresses is disabled.

When SER1_ADDR is not 0FFH and bLCR_PAR_EN = 1, the automatic comparison of the bus address is enabled, and the following parameters should be configured: bLCR_WORD_SZ1 and bLCR_WORD_SZ0 are both 1 to select 8 data bits. BLCR_PAR_MOD1 is always 1. For the address byte is MARK In the case where bit 9 of the data byte is 0, bLCR_PAR_MOD0 should be set to 1.For the case where the address byte is SPACE (that is, bit 9 of the data byte is 1), bLCR_PAR_MOD0 should be set to 0, that is, select according to the data byte.

UART1 baud rate divisor latch (SER1_DLM, SER1_DLL), only valid when bLCR_DLAB = 1:

Bit	Name	Access	Description	Reset value
[7:0]	SER1_DLL	RW	SER1_DLL is the low byte and SER1_DLM is the high byte. The two form a 16-bit divisor and are used for a serial baud rate generator composed of a 16-bit counter. These registers can only be read and written when bLCR_DLAB is 1. The divisor = Fsys * 2 / SER1_DIV / 16 / baud rate	xxh
[7:0]	SER1_DLM	RW		80h

UART1 prescaler divisor register (SER1_DIV), only valid when bLCR_DLAB = 1:

Bit	Name	Access	Description	Reset value
[7:0]	SER1_DIV	RW	It is used to multiply the system main clock Fsys and then pre-divide to generate the internal reference clock of the serial port baud rate generator. This register can only be read and written when bLCR_DLAB is 1	xxh

13.3 UART Application

UART0 application:

Select the baud rate generator of UART0, you can choose from timer T1 or T2, and configure the corresponding counter.
Start the timer.
Set SM0, SM1, and SM2 of SCON to select the working mode of serial port 0. Set REN to 1 to enable UART0 reception.
You can set the serial port interrupt or query the RI and TI interrupt status.
Read and write SBUF implements serial data transmission and reception, the allowable baud rate error of the serial port receiving signal is not greater than 2%.

UART1 application:

Set the bit bLCR_DLAB of SER1_LCR to 1, write the UART1 prescaler register SER1_DIV, calculate the baud rate divisor according to the baud rate, the divisor = Fsys / 8 / SER1_DIV / baud rate, and the high n. low bytes of the divisor are written to SER1_DLM And SER1_DLL.
Set SER1_LCR, select the appropriate serial data format, data byte, and parity mode.
Optional setting SER1_IER, select UART1 interrupt status trigger.
If the interrupt mode is used, the bit bMCR_OUT2 of SER1_MCR needs to be set to 1 to enable the interrupt output; otherwise, the interrupt status bit needs to be queried actively.
Read and write SER1_FIFO to realize serial data transmission and reception, the allowable baud rate error of the serial port receiving signal is not greater than 2%.