15. Analog-to-digital converter ADC

15.1 ADC Introduction

The CH559 chip provides 10-bit or 11 optional successive approximation analog-to-digital converters. The converter has 8 analog signal input channels, which can be time-sharing acquisition.

ADC main features:

Select 10-bit or 11-bit resolution.
ADC analog input voltage range: 0 to VDD33.
Maximum 1MSPS sampling rate.
Supports automatic alternate channel mode for automatic alternate conversion between two input channels.
Built-in 2-level FIFO, supporting automatic sampling and DMA.

15.2 ADC Register

Table 15.2.1 ADC related register list

Name	Address	Description	Reset value
ADC_EX_SW	F7h	ADC extended analog switch control register	00h
ADC_SETUP	F6h	ADC setting register	08h
ADC_FIFO_H	F5h	FIFO high byte of ADC (read only)	0xh
ADC_FIFO_L	F4h	FIFO low byte of ADC (read only)	xxh
ADC_FIFO	F4h	ADC_FIFO_L and ADC_FIFO_H form a 16-bit SFR	0xxxh
ADC_CHANN	F3h	ADC channel selection register	00h
ADC_CTRL	F2h	ADC control register	00h
ADC_STAT	F1h	ADC status register	04h
ADC_CK_SE	EFh	ADC clock division setting register	10h
ADC_DMA_CN	EEh	DMA Remaining Count Register	00h
ADC_DMA_AH	EDh	DMA current buffer address high byte	0xh
ADC_DMA_AL	ECh	DMA current buffer address low byte	xxh
ADC_DMA	ECh	ADC_DMA_AL and ADC_DMA_AH form a 16-bit SFR	0xxxh

DMA current buffer address (ADC_DMA):

Bit	Name	Access	Description	Reset value
[7:0]	ADC_DMA_AH	RW	The current high byte of the DMA address, which can be preset to the initial value. It automatically increases after DMA. Only the lower 4 bits are valid. The upper 4 bits are fixed at 0. Only the first 4K of xRAM are supported.	0xh
[7:0]	ADC_DMA_AL	RW	Low byte of the current DMA address, which can be preset to the initial value. It is automatically increased after DMA. Only the upper 7 bits are valid. The lowest bit is fixed at 0. Only even addresses are supported.	xxh

DMA Remaining Count Register (ADC_DMA_CN):

Bit	Name	Access	Description	Reset value
[7:0]	ADC_DMA_CN	RW	The current remaining DMA count, which can be preset to the initial value, and is automatically reduced after the DMA operation	00h

Clock divider setting register (ADC_CK_SE):

Bit	Name	Access	Description	Reset value
7	bADC_CHK_CLK_SEL	RW	AIN7 level detection delay clock frequency selection, if this bit is 0, low speed 1x clock frequency. If this bit is 1, high speed 4x clock frequency	0
[6:0]	MASK_ADC_CK_SE	RW	ADC clock division factor to set the internal ADC working clock	10h

ADC status register (ADC_STAT):

Bit	Name	Access	Description	Reset value
7	bADC_IF_DMA_END	RW	DMA complete interrupt flag. A 1 in this bit indicates an interrupt; a 0 in this bit indicates no interrupt. Cleared on write 1 or cleared on ADC_DMA_CN	0
6	bADC_IF_FIFO_OV	RW	This bit is 1 to indicate FIFO overflow interrupt; if this bit is 0, there is no interrupt. Write 1 clear	0
5	bADC_IF_AIN7_LOW	RW	This bit is 1 to indicate that the AIN7 low-level interrupt was detected.	0
4	bADC_IF_ACT	RW	This bit is 1 to indicate an ADC conversion completion interrupt. Write 1 to clear it.	0
3	bADC_AIN7_INT	R0	This bit is 1 to indicate the delay state of the AIN7 input low level	0
2	bADC_CHANN_ID	R0	is the current channel identification flag in the automatic alternate channel mode. 0 means AIN0 or AIN6. 1 means AIN1 or AIN4 or AIN7	0
2	bADC_DATA_OK	RO	In the manual channel selection mode, the ADC conversion is completed and the result is ready. A 1 indicates that the ADC data is ready and the ADC converter is idle. A 0 indicates that the ADC is in progress and the data is not ready.	1
[1:0]	MASK_ADC_FIFO_CNT	R0	ADC FIFO current count	00b

MASK_ADC_FIFO_CNT consists of bADC_FIFO_CNT1 and bADC_FIFO_CNT0, which is used to display the ADC’s FIFO count.

MASK_ADC_FIFO_CNT	Description
00b	FIFO is empty.If the FIFO is read, it will directly return the current ADC result value.
01b	1 data in FIFO
10b	FIFO is full, there are 2 data in FIFO
11b	unknown error

ADC Control Register (ADC_CTRL):

Bit	Name	Access	Description	Reset value
7	bADC_SAMPLE	RW	In the manual sampling mode, it is the sampling control bit. Set it first and then clear it to 0 to generate a high-level pulse to start the ADC once. In the automatic sampling mode, it is the sampling pulse state of automatic sampling.	0
6	bADC_SAMP_WIDTH	RW	Sampling pulse width control bit in auto sampling mode, 0 for 1 ADC clock width; 1 for 2 ADC clock width	0
5	bADC_CHANN_MOD1	RW	ADC channel mode high	0
4	bADC_CHANN_MOD0	RW	ADC channel mode low	0
[3:0]	MASK_ADC_CYCLE	RW	ADC running cycle number, 0 means manual sampling; non-zero value means setting the running cycle of automatic sampling (counted by ADC clock)	0000b

MASK_ADC_CHANN consisting of bADC_CHANN_MOD1 and bADC_CHANN_MOD0 is the ADC channel control mode flag.

MASK_ADC_CHANN	Description
00b	Manually select channel mode, set ADC_CHANN to select current input channel
01b	Auto alternate channel mode, switch between AIN0 and AIN1 automatically
10b	Auto Alternate Channel Mode, automatically alternate between AIN6 and AIN4
11b	Auto Alternate Channel Mode, automatically alternate between AIN6 and AIN7

ADC channel selection register (ADC_CHANN):

Bit	Name	Access	Description	Reset value
[7:0]	ADC_CHANN	RW	Select the current ADC analog input channel, select one from the 8 channels, bits 0~7 correspond to AIN0~AIN7 respectively	00h

ADC’s FIFO port (ADC_FIFO):

Bit	Name	Access	Description	Reset value
[7:0]	ADC_FIFO_H	RO	ADC FIFO high byte, only the lower 4 bits are valid, the upper 4 bits are fixed to 0	0xh
[7:0]	ADC_FIFO_L	RO	ADC FIFO low byte	xxh

ADC setup register (ADC_SETUP):

Bit	Name	Access	Description
7	bADC_DMA_EN	RW	This bit is 1 to enable the DMA and DMA interrupts of the ADC. 0 to disable the enable
6	bADC_IE_FIFO_OV	RW	This bit is 1 to enable the FIFO overflow interrupt. This bit is 0 to disable the enable
5	bADC_IE_AIN7_LOW	RW	This bit is 1 to enable detection of AIN7 low-level interrupt
4	bADC_IE_ACT	RW	This bit is 1 to enable the ADC conversion completion interrupt. This bit is 0 to disable the enable
3	bADC_CLOCK	RO	Current level of the internal ADC clock signal
2	bADC_POWER_EN	RW	ADC power control bit of the sampling conversion module. This bit is 0 to turn off the power of the ADC module and enter the sleep state. A bit of 1 to turn on
1	bADC_EXT_SW_EN	RW	Power control bit of the extended analog switch module. This bit is 0 to disable the extended analog switch module. 1 to enable the bit.
0	bADC_AIN7_CHK_EN	RW	Detect the power control bit of AIN7 low-level module. This bit is 0 to disable detection of AIN7 low-level module. 1 to enable

ADC extended analog switch control register (ADC_EX_SW):

Bit	Name	Access	Description
7	bADC_SW_AIN7_H	RW	AIN7 channel internal analog switch connection control, this bit is 1 internally connects AIN7 to VDD33. This bit is 0 to disconnect AIN7 from VDD33
6	bADC_SW_AIN6_L	RW	AIN6 channel internal analog switch connection control, this bit is 1 internally connects AIN6 to GND. This bit is 0 to disconnect AIN6 from GND
5	bADC_SW_AIN5_H	RW	AIN5 channel internal analog switch connection control, this bit is 1 internally connects AIN5 to VDD33. This bit is 0 to disconnect AIN5 and VDD33
4	bADC_SW_AIN4_L	RW	AIN4 channel internal analog switch connection control, this bit is 1 internally connects AIN4 to GND. This bit is 0 to disconnect AIN4 from GND
3	bADC_EXT_SW_SEL	RW	On-resistance value selection bit of the internal analog switch. This bit is 0 to select high resistance, about 800Ω. This bit is 1 to select low resistance, about 300Ω
2	bADC_RESOLUTION	RW	ADC resolution selection bit, this bit is 0 to select 10-bit resolution. This bit is 1 to select 11-bit resolution
1	bADC_AIN7_DLY1	RW	Delay control bit for detecting AIN7 low level 1
0	bADC_AIN7_DLY0	RW	Delay control bit for detecting AIN7 low level 0

bADC_AIN7_DLY1 and bADC_AIN7_DLY0 form MASK_ADC_AIN7_DLY, which is used to select the delay after detecting the level change of AIN7: 00 is no delay, 01 is the longest delay, 10 is the longer delay, and 11 is the shorter delay.

15.3 ADC Functions

ADC sampling mode configuration steps:

Set the bADC_POWER_EN bit in the ADC setting register ADC_SETUP to 1 to enable the ADC module.
Set the clock divider setting register ADC_CK_SE, select the clock frequency, the highest frequency is 12MHz, and it is recommended not to be lower than 1MHz.
Clear the existing data in the FIFO. If you need to use interrupt or DMA, then make the relevant settings here.
For the automatic sampling mode, the ADC channel selection register ADC_CHANN should be set first.
Set bADC_SAMPLE and MASK_ADC_CYCLE in the ADC control register ADC_CTRL.If MASK_ADC_CYCLE is set to 0, it is a manual sampling mode.If MASK_ADC_CYCLE is set to a non-zero value, it is an automatic sampling mode.At this time, MASK_ADC_CYCLE is a continuous and automatic sampling. Clock cycle.
For the manual sampling mode, set the ADC channel selection register ADC_CHANN to select the ADC analog signal input channel.
If it is in manual sampling mode, you need to set the bADC_SAMPLE bit to 1 and clear it after delaying at least one ADC clock cycle to complete an analog signal sampling and start an ADC conversion.
Wait for the bADC_IF_ACT bit in the ADC status register ADC_STAT to be 1, indicating that the ADC conversion is complete, and the result data can be read through the ADC_FIFO.
Or read MASK_ADC_FIFO_CNT of ADC status register ADC_STAT to get the FIFO count, and then read some data through ADC_FIFO. It is recommended to discard the first ADC result data, because there may be incomplete sampling.
For DMA steps: Set ADC_DMA as the start address value of the user-defined data buffer, set ADC_DMA_CN as the user-defined DMA remaining count, and set the bADC_DMA_EN bit in ADC_SETUP to 1 to enable the DMA function.
There are 12 bits of ADC result data, among which bits 0 ~ 10 are ADC values, bits 11 are flag bits, bits 12 ~ 15 are always 0. For manual channel selection mode, bit 11 is always 0; for automatic alternate channel mode, bit 11 indicates the channel identification flag of the ADC value, refer to bADC_CHANN_ID description.