8-bit enhanced USB microcontroller CH559
4. Pin descriptions
CH559L/T pin definitions.
| Pin number | Pin name (function after reset) | Alternate functions | Alternate functions description | |
|---|---|---|---|---|
| SSOP-20 | LQFP-48 | |||
| 19 | 41 | VIN5 | V5 | The 5V external power input of the internal 5V->3.3V voltage regulator requires an external 0.1uF power supply decoupling capacitor. |
| 20 | 42 | VDD33 | VDD/VCC | Internal voltage regulator output and internal 3.3V working power input. When the power supply voltage is less than 3.6V, connect VIN5 to input external power supply. When the power supply voltage is greater than 3.6V, connect 3.3uF power supply decoupling capacitor. |
| 18 | 18 | GND | VSS | Common ground terminal. |
| -- | 40 | P0.0 | AD0/UDTR | P0 port: The default is an 8-bit open-drain bidirectional port. You can enable the internal pull-up resistor to be turned into a quasi-bidirectional port by setting P0_PU. P0 temporarily switches to push-pull output as a bidirectional data bus AD0~AD7 when accessing the external bus, or outputs the lower 8 bits of the address as needed when accessing the external bus in multiplexed address mode. UDTR, URTS: Modem signal output of UART1. UCTS, UDSR, URI, UDCD: UART1 modem signal input. RXD_, TXD_: RXD, TXD pin mapping. |
| -- | 39 | P0.1 | AD1/URTS | |
| 17 | 38 | P0.2 | AD2/RXD_ | |
| 16 | 37 | P0.3 | AD3/TXD_ | |
| -- | 36 | P0.4 | AD4/UCTS | |
| -- | 35 | P0.5 | AD5/UDSR | |
| -- | 34 | P0.6 | AD6/URI | |
| -- | 33 | P0.7 | AD7/UDCD | |
| -- | 43 | P1.0 | AIN0/T1/CAP1 | AIN0~AIN7: 8-channel ADC analog signal input. T2: External count input/clock output of timer/counter 2. T2EX: Timer/Counter 2 Reload/Capture Input. CAP1, CAP2: Capture input of timer/counter 2 1, 2. CAP3/PWM3: Timer/Event Counter 3 Capture Input/PWM Output. SCS, MOSI, MISO, SCK: SPI0 interface, SCS is the chip select input, MOSI is the master output/slave input, MISO is the master input/slave output, and SCK is the serial clock. |
| -- | 44 | P1.1 | AIN1/T2EX/CAP2 | |
| 1 | 45 | P1.2 | AIN2/PWM3/CAP3 | |
| -- | 46 | P1.3 | AIN3 | |
| 2 | 47 | P1.4 | AIN4/SCS | |
| 3 | 48 | P1.5 | AIN5/MOSI | |
| 4 | 1 | P1.6 | AIN6/MISO | |
| 5 | 2 | P1.7 | AIN7/SCK | |
| -- | 21 | P2.0 | A8 | When P2 accesses the external bus, it will automatically switch to the push-pull output temporarily, and output the upper 8 bits of the address A8~A15 as needed. MOSI1, MISO1, SCK1: SPI1 interface, MOSI1 is the master output, MISO1 is the master input, and SCK1 is the serial clock output. PWM1, PWM2: PWM1 output, PWM2 output. TNOW: UART1 is sending an output indication. T2EX_/CAP2_: T2EX/CAP2 pin mapping. RXD1, TXD1: UART1 serial data input, serial data output. DA7: Output address A7 when accessing the external bus in direct address mode. |
| -- | 22 | P2.1 | MOSI1/A9 | |
| -- | 23 | P2.2 | MISO1/A10 | |
| -- | 24 | P2.3 | SCK1/A11 | |
| -- | 25 | P2.4 | PWM1/A12 | |
| 11 | 26 | P2.5 | TNOW/PWM2/A13/T2EX_/CAP2_ | |
| 12 | 27 | P2.6 | RXD1/A14 | |
| 13 | 28 | P2.7 | TXD1/DA7/A15 | |
| -- | 4 | P3.0 | RXD | RXD, TXD: UART0 serial data input, serial data output. INT0, INT1: External interrupt 0, External interrupt 1 input. LED0, LED1, LEDC: LED serial data 0, 1, clock output. !A15: External bus address A15 Inverting output for chip select. T0, T1: Timer 0, Timer 1 External input. XCS0: External bus address 4000h~7FFFh Chip select output. DA6: Output address A6 when accessing the external bus in direct address mode. WR, RD: External bus write signal, read signal. |
| -- | 7 | P3.1 | TXD | |
| 7 | 8 | P3.2 | LED0/INT0 | |
| -- | 9 | P3.3 | LED1/!A15/INT1 | |
| 8 | 10 | P3.4 | LEDC/XCS0/T0 | |
| -- | 11 | P3.5 | DA6/T1 | |
| -- | 12 | P3.6 | WR | |
| -- | 13 | P3.7 | RD | |
| -- | 20 | P4.0 | LED2/A0/RXD1_ | A0~A5: Outputs the lower 6-bit address A0~A5 when accessing the external bus in direct address mode. LED2, LED3: LED serial data 2, 3 output. RXD1_, TNOW_/TXD1_: RXD1, TNOW/TXD1 pin mapping. PWM3_/CAP3_: PWM3/CAP3 pin mapping. PWM1_, PWM2_: PWM1, PWM2 pin mapping. XI, XO: external crystal oscillator input, inverting output. SCS_, SCK_: SPI0 Chip Select SCS, SCK pin mapping. |
| -- | 19 | P4.1 | A1 | |
| -- | 15 | P4.2 | PWM3_/CAP3_/A2 | |
| -- | 14 | P4.3 | PWM1_/A3 | |
| -- | 6 | P4.4 | LED3/TNOW_/TXD1_/A4 | |
| -- | 5 | P4.5 | PWM2_/A5 | |
| 9 | 16 | P4.6 | XI/SCS_ | |
| 10 | 17 | P4.7 | X0/SCK_ | |
| 15 | 32 | P5.0 | DM | DM, DP: USB host HUB0 or D-, D+ signal terminal of USB device. |
| 14 | 31 | P5.1 | DP | |
| -- | 30 | P5.4 | HM/ALE/XB | XB, XA: B/inverting, A/in-phase signal terminal of iRS485. ALE: Address latch signal output in multiplexed address mode. !A15: External bus address A15 Inverting output for chip select. HM, HP: The USB host extends the D- and D+ signals of HUB1. |
| -- | 29 | P5.5 | HP/!A15/XA | |
| 6 | 3 | P5.7 | RST | External reset input with built-in pull-down resistor. |