7. Power management, sleep and reset

7.1 External power input

The CH559 chip has an internal working voltage of 3.3V, and the input/output voltage of the I/O pin is 3.3V. The I/O pins except P1.0~P1.7, XI, XO, and RST can withstand 5V voltage input. The CH559 chip has a 5V to 3.3V low dropout voltage regulator that supports an external 3.3V or 5V supply voltage input. The two supply voltage input modes refer to the table below.

External supply voltage	VIN5 pin voltage: external voltage 3.3V~5V	VDD33 pin voltage: internal voltage 3.3V
3.3V includes less than 3.6V	Input external 3.3V voltage to voltage regulator, must be grounded to not less than 0.1uF decoupling capacitor	Input external 3.3V as internal working power supply, must be grounded to ground not less than 0.1uF decoupling capacitor
5V includes greater than 3.6V	Input external 5V voltage to voltage regulator, must be grounded to not less than 0.1uF decoupling capacitor	Internal voltage regulator 3.3V output and 3.3V internal working power input, must be grounded to not less than 3.3uF decoupling capacitor

After the power is turned on or the system is reset, the CH559 is running by default. When some function modules are not needed, the clocks of these modules can be turned off to reduce power consumption. When the CH559 does not need to run at all, the PD in the PCON can be set to sleep. In the sleep state, external wake-up can be selected via USB, UART0, UART1, SPI0 and some GPIOs.

7.2 Power and Sleep Control Registers

Table 7.2.1 List of Power and Sleep Control Registers

Name	Address	Description	Reset value
WDOG_COUNT	FFh	Watchdog Count Register	00h
RESET_KEEP	FEh	reset holding register	00h
WAKE_CTRL	EBh	Sleep Wake Control Register	00h
SLEEP_CTRL	EAh	Sleep control register	00h
PCON	87h	Power Control Register	10h

Watchdog Count Register (WDOG_COUNT):

Bit	Name	Access	Description	Reset value
[7:0]	WDOG_COUNT	RW	The current count of the watchdog is 0FFh. It overflows when it is 00h. When it overflows, it automatically sets the interrupt flag bWDOG_IF_TO to 1	00h

Reset holding register (RESET_KEEP):

Bit	Name	Access	Description	Reset value
[7:0]	RESET_KEEP	RW	Reset the holding register, the value can be modified manually, except for the power-on reset to clear it, any other reset does not affect the value	00h

Sleep wake control register (WAKE_CTRL), which can be written only in safe mode:

Bit	Name	Access	Description
7	bWAK_BY_USB	RW	USB event wake-up enable, this bit is 0, no wake-up is allowed
6	bWAK_RXD1_LO	RW	UART1 receives an input low wake-up enable. This bit is 0 to disable wake-up. Select XA/XB differential input in iRS485 mode, select RXD1 or RXD1_ pin according to bIER_PIN_MOD1=1/0 in non-iRS485 mode
5	bWAK_P1_5_LO	RW	P1.5 low wake enable, 0 disable wakeup
4	bWAK_P1_4_LO	RW	P1.4 Low wake enable, 0 disable wakeup
3	bWAK_P0_3_LO	RW	P0.3 Low wake enable, 0 disable wakeup
2	bWAK_CAP3_LO	RW	Timer3 captures the input low wake enable, and 0 disables wakeup. Select CAP3 or CAP3_ pin according to bTMR3_PIN_X=0/1
1	bWAK_P3_2E_3L	RW	P3.2 Edge change and P3.3 low wake enable, 0 disable wakeup
0	bWAK_RXD0_LO	RW	UART0 receives input low wake enable, 0 disables wakeup. Select RXD0 or RXD0_ pin according to bUART0_PIN_X=0/1

Sleep Control Register (SLEEP_CTRL), which can be written only in Safe Mode:

Bit	Name	Access	Description
7	bSLP_OFF_USB	RW	USB clock off control, this bit is 1 Off clock
6	bSLP_OFF_ADC	RW	ADC clock off control, this bit is 1 Off clock
5	bSLP_OFF_UART1	RW	UAR1 clock off control, this bit is 1 off clock
4	bSLP_OFF_P1S1	RW	PWM1 and SPI1 clock off control, this bit is 1 OFF clock
3	bSLP_OFF_SPI0	RW	SPI0 clock off control, this bit is 1 off clock
2	bSLP_OFF_TMR3	RW	Timer3 clock off control, this bit is 1 off clock
1	bSLP_OFF_LED	RW	LED-CTRL Clock off control, this bit is 1 Off clock
0	bSLP_OFF_XRAM	RW	xRAM clock off control, this bit is 1 off clock

Power Control Register (PCON):

Bit	Name	Access	Description	Reset value
7	SMOD	RW	When using Timer 1 to generate UART0 baud rate, select the communication baud rate of UART0 mode 1, 2, 3: 0-slow mode; 1-fast mode	0
6	reserved	RO	reserved	0
5	bRST_FLAG1	R0	chip last reset flag high	0
4	bRST_FLAG0	R0	chip last reset flag low	1
3	GF1	RW	universal flag 1: User can define it by itself, can be cleared or set by software.	0
2	GF0	RW	general flag 0: user can define it himself, can be cleared or set by software	0
1	PD	RW	sleep mode enable, set to sleep after 1 wake-up hardware automatically cleared	0
0	reserved	R0	reserved	0

Table 7.2.2 Description of the chip's last reset flag

bRST_FLAG1	bRST_FLAG0	Reset flag description
0	0	Software reset, source: bSW_RESET=1 and (bBOOT_LOAD=0 or bWDOG_EN=1)
0	1	Power-on reset, source: VDD33 pin voltage is lower than detection level
1	0	Watchdog reset, source: bWDOG_EN=1 and watchdog timeout
1	1	External pin is manually reset, source: En_P5.7_RESET=1 and P5.7 input high

7.3 Reset Control

The CH559 has four reset sources: power-on reset, external reset, software reset, watchdog reset, and the latter three are hot resets.

7.3.1 Power-on reset

Power-on reset POR is generated by the on-chip voltage detection circuit. The POR circuit continuously monitors the supply voltage of the VDD33 pin. Below the detection level, Vpot generates a power-on reset, and the hardware automatically delays Tpor to maintain the reset state. After the delay expires, CH559 runs. Only the power-on reset causes the CH559 to reload the configuration information and clear RESET_KEEP. Other thermal resets do not affect.

7.3.2 External reset

An external reset is generated by a high level applied to the RST pin. The reset process is triggered when the configuration information En_P5.7_RESET is 1 and the high level on the RST pin lasts longer than Trst. When the external high level signal is cancelled, the hardware automatically delays Trdl to maintain the reset state. After the delay expires, CH559 starts from the 0 address.

7.3.3 Software Reset

The CH559 supports an internal software reset to actively reset the CPU state and re-run without external intervention. Set bSW_RESET in the global configuration register GLOBAL_CFG to 1, software reset, and automatically delay Trdl to maintain the reset state. After the delay expires, CH559 starts from 0 address, and bSW_RESET bit is automatically cleared by hardware.

When bSW_RESET is set, if bBOOT_LOAD=0 or bWDOG_EN=1, bRST_FLAG1/0 will be indicated as a software reset after reset; when bSW_RESET is set to 1, if bBOOT_LOAD=1 and bWDOG_EN=0, then bRST_FLAG1/0 will not generate new The reset flag, but keeps the previous reset flag unchanged.

For a chip with an ISP boot program, after the power-on reset, run the boot program, which resets the chip to the application state according to the software reset. This software reset only causes bBOOT_LOAD to be cleared, and does not affect the state of bRST_FLAG1/0. (Because bBOOT_LOAD=1 before reset), when switching to the application state, bRST_FLAG1/0 still indicates the power-on reset state.

7.3.4 Watchdog Reset

The watchdog reset is generated when the watchdog timer times out. The watchdog timer is an 8-bit counter that counts the clock frequency of the system’s main frequency, Fsys/262144. When the 0FFh is turned to 00h, an overflow signal is generated.

The watchdog timer overflow signal will trigger the interrupt flag bWDOG_IF_TO to be 1, which is automatically cleared when the WDOG_COUNT is reloaded or when the corresponding interrupt service routine is entered.

Different timing periods Twdc are achieved by writing different count initial values to WDOG_COUNT. At 12MHz, the watchdog timing period Twdc at 00h is about 5.9 seconds and about 2.8 seconds at 80h.

If bWDOG_EN = 1 when the watchdog timer overflows, a watchdog reset is generated, and Trdl is automatically delayed to maintain the reset state. After the delay is over, CH559 starts from the 0 address.

To avoid being reset by the watchdog when bWDOG_EN=1, WDOG_COUNT must be reset in time to avoid overflow.