9. Interrupt
The CH559 chip supports 14 sets of interrupt signal sources, including 6 sets of interrupts compatible with the standard MCS51: INT0, T0, INT1, T1, UART0, T2, and extended 8 sets of interrupts: SPI0, TMR3, USB, ADC, UART1, PWM1 GPIO, WDOG, among which GPIO interrupt can be selected from 7 I/O pins.
9.1 Register description
Table 9.1.1 Interrupt vector table
| Interrupt Source | Entry Address | Interrupt number | Description | Default priority |
|---|---|---|---|---|
| INT_NO_INT0 | 0x0003 | 0 | External interrupt 0 or LED control card interrupt: When bLED_OUT_EN = 0 is external interrupt 0; When bLED_OUT_EN = 1 is LED control card interrupt | High priority ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Low priority |
| INT_NO_TMR0 | 0x000B | 1 | Timer 0 interrupt | |
| INT_NO_INT1 | 0x0013 | 2 | External interrupt 1 | |
| INT_NO_TMR1 | 0x001B | 3 | Timer 1 interrupt | |
| INT_NO_UART0 | 0x0023 | 4 | UART0 interrupt | |
| INT_NO_TMR2 | 0x002B | 5 | Timer 2 interrupt | |
| INT_NO_SPI0 | 0x0033 | 6 | SPI0 interrupt | |
| INT_NO_TMR3 | 0x003B | 7 | Timer 3 interrupt | |
| INT_NO_USB | 0x0043 | 8 | USB interrupt | |
| INT_NO_ADC | 0x004B | 9 | ADC interrupt | |
| INT_NO_UART1 | 0x0053 | 10 | UART1 interrupt | |
| INT_NO_PWM1 | 0x005B | 11 | PWM1 interrupt | |
| INT_NO_GPIO | 0x0063 | 12 | GPIO interrupt | |
| INT_NO_WDOG | 0x006B | 13 | Watchdog timer interrupt |
Table 9.1.2 Interrupt related register list
| Name | Address | Description | Reset value |
|---|---|---|---|
| IP_EX | E9h | Extended interrupt priority control register | 00h |
| IE_EX | E8h | Extended interrupt enable register | 00h |
| GPIO_IE | CFh | GPIO interrupt enable register | 00h |
| IP | B8h | Interrupt Priority Control Register | 00h |
| IE | A8h | interrupt enable register | 00h |
Interrupt Enable Register (IE):
| Bit | Name | Access | Description | Reset value |
|---|---|---|---|---|
| 7 | EA | RW | Global interrupt enable control bit, this bit is 1 and E_DIS is 0 to enable interrupts. this bit is 0 to mask all interrupt requests | 0 |
| 6 | E_DIS | RW | Global interrupt disable control bit, this bit is 1 to mask all interrupt requests. this bit is 0 and EA is 1 to enable interrupts. This bit is typically used to temporarily disable interrupts during flash-ROM operations | 0 |
| 5 | ET2 | RW | Timer 2 interrupt enable bit, this bit is 1 to enable T2 interrupt. it is 0 to mask | 0 |
| 4 | ES | RW | Asynchronous serial port 0 interrupt enable bit, this bit is 1 to enable UART0 interrupt. masked to 0 | 0 |
| 3 | ET1 | RW | Timer 1 interrupt enable bit. This bit is 1 to enable the T1 interrupt. it is masked to 0. | 0 |
| 2 | EX1 | RW | External interrupt 1 enable bit, this bit is 1 to enable the INT1 interrupt. masked to 0 | 0 |
| 1 | ET0 | RW | Timer 0 interrupt enable bit, this bit is 1 to enable the T0 interrupt. masked to 0 | 0 |
| 0 | EX0 | RW | External interrupt 0 and LED control card interrupt enable bit, this bit is 1 to enable INT0 / LED interrupt, selected by bLED_OUT_EN. masked to 0 | 0 |
Extended interrupt enable register (IE_EX):
| Bit | Name | Access | Description | Reset value |
|---|---|---|---|---|
| 7 | IE_WDOG | RW | Watchdog timer interrupt enable bit, this bit is 1 to enable WDOG interrupt; 0 to mask | 0 |
| 6 | IE_GPIO | RW | GPIO interrupt enable bit, this bit is 1 to enable interrupts enabled in GPIO_IE; 0 to mask all interrupts in GPIO_IE | 0 |
| 5 | IE_PWM1 | RW | PWM1 interrupt enable bit. This bit is 1 to enable PWM1 interrupt; 0 to mask 0 | 0 |
| 4 | IE_UART1 | RW | asynchronous serial port 1 interrupt enable bit, this bit is 1 to enable UART1 interrupt; 0 to mask | 0 |
| 3 | IE_ADC | RW | ADC analog-to-digital conversion interrupt enable bit, this bit is 1 to enable ADC interrupt; 0 to mask | 0 |
| 2 | IE_USB | RW | USB interrupt enable bit, this bit is 1 to enable USB interrupt; 0 to mask | 0 |
| 1 | IE_TMR3 | RW | Timer 3 interrupt enable bit, this bit is 1 to enable Timer3 interrupt; 0 to mask | 0 |
| 0 | IE_SPI0 | RW | SPI0 interrupt enable bit, this bit is 1 to enable SPI0 interrupt; 0 to mask | 0 |
GPIO interrupt enable register (GPIO_IE):
| Bit | Name | Access | Description | Reset value |
|---|---|---|---|---|
| 7 | bIE_IO_EDGE | RW | GPIO edge interrupt mode enable: This bit is 0 to select the level interrupt mode.If the GPIO pin input valid level, bIO_INT_ACT is 1 and the interrupt is always requested.When the GPIO input invalid level, bIO_INT_ACT is 0 and the interrupt request is canceled. This bit is 1 to select the edge interrupt mode. When a valid edge is input to the GPIO pin, the interrupt flag bIO_INT_ACT is generated and an interrupt is requested. This interrupt flag cannot be cleared by software. It can only be reset or in level interrupt mode or enter the corresponding interrupt service routine Is automatically cleared | 0 |
| 6 | bIE_RXD1_LO | RW | This bit is 1 to enable UART1 receive pin interrupt (level mode is active low, edge mode falling edge is active). this bit is 0 to disable. Select XA/XB differential input in iRS485 mode, select RXD1 or RXD1_ pin according to bIER_PIN_MOD1 = 1/0 in non-iRS485 mode | 0 |
| 5 | bIE_P5_5_HI | RW | This bit is 1 to enable the P5.5 interrupt (level mode is active high and edge mode is active on rising edge); this bit is 0 to disable | 0 |
| 4 | bIE_P1_4_LO | RW | This bit is 1 to enable the P1.4 interrupt (level mode is active low, edge mode is active on falling edge); this bit is 0 to disable | 0 |
| 3 | bIE_P0_3_LO | RW | This bit is 1 to enable the P0.3 interrupt (active in low level in level mode and valid in falling edge in edge mode); this bit is 0 to disable | 0 |
| 2 | bIE_P5_7_HI | RW | This bit is 1 to enable the P5.7 interrupt (level mode is active high and edge mode is active on rising edge); this bit is 0 to disable | 0 |
| 1 | bIE_P4_1_LO | RW | This bit is 1 to enable the P4.1 interrupt (active in low level in level mode and valid in falling edge in edge mode); this bit is 0 to disable | 0 |
| 0 | bIE_RXD0_LO | RW | This bit is 1 to enable the UART0 receive pin interrupt (level mode is active low, edge mode is active falling edge); this bit is 0 to disable. Select RXD0 or RXD0_ pin according to bUART0_PIN_X = 0/1 | 0 |
Interrupt Priority Control Register (IP):
| Bit | Name | Access | Description | Reset value |
|---|---|---|---|---|
| 7 | PH_FLAG | R0 | High priority interrupt executing flag | 0 |
| 6 | PL_FLAG | R0 | Low Priority Interrupt Execution Flag | 0 |
| 5 | PT2 | RW | Timer 2 interrupt priority control bit | 0 |
| 4 | PS | RW | UART0 interrupt priority control bit | 0 |
| 3 | PT1 | RW | Timer 1 interrupt priority control bit | 0 |
| 2 | PX1 | RW | Interrupt priority control bit for external interrupt 1 | 0 |
| 1 | PT0 | RW | timer 0 interrupt priority control bit | 0 |
| 0 | PX0 | RW | External Interrupt 0 and Interrupt Priority Control Bit for LED Control Card Interrupt | 0 |
Extended interrupt priority control register (IP_EX):
| Bit | Name | Access | Description | Reset value |
|---|---|---|---|---|
| 7 | bIP_LEVEL | R0 | Current interrupt nesting level flag bit. If this bit is 0, it means no interrupt or nested level 2 interrupt.If this bit is 1, it means current nested level 1 interrupt. | 0 |
| 6 | bIP_GPIO | RW | GPIO interrupt priority control bit | 0 |
| 5 | bIP_PWM1 | RW | PWM1 interrupt priority control bit | 0 |
| 4 | bIP_UART1 | RW | UART1 interrupt priority control bit | 0 |
| 3 | bIP_ADC | RW | ADC interrupt priority control bit | 0 |
| 2 | bIP_USB | RW | USB interrupt priority control bit | 0 |
| 1 | bIP_TMR3 | RW | Timer3 interrupt priority control bit | 0 |
| 0 | bIP_SPI0 | RW | SPI0 interrupt priority control bit | 0 |
The IP and IP_EX registers are used to set the interrupt priority. If a bit is set to 1, the corresponding interrupt source is set to a high priority. If a bit is cleared to 0, the corresponding interrupt source is set to a low priority . For the same level interrupt source, the system has a default priority order. The default priority order is shown in Table 9.1.1. Its PH_FLAG and PL_FLAG combination indicates the priority of the current interrupt.
Table 9.1.3 Current interrupt priority status indication
| PH_FLAG | PL_FLAG | Current interrupt priority status |
|---|---|---|
| 0 | 0 | No interruption currently |
| 0 | 1 | Low priority interrupt is currently executing |
| 1 | 0 | High priority interrupt is currently executing |
| 1 | 1 | Unexpected state, unknown error |